CS 2734 Computer Organization II

• Clocks -- the basic idea of how clocked circuits work, with a latched state element feeding into combinational logic, which in turn feeds in a loop back to the latched state element for the next clock cycle.
  • Section B.4, pages B-18 to B-21.
  • Chapter 5, pages 341-343.

• Datapath Overview (Sections 5.1 and 5.2). Rough organization and components, including
  • Instruction Register (Not a true component in the single-cycle implementation -- see below.)
  • Instruction Memory (Read-only, for instructions.)
  • Register File (Read and write the 32 registers.)
  • ALU (Combinational logic to do arithmetic.)
  • Data Memory (Read and write memory.)

• Single-cycle Implementation (Section 5.3) Note: Labs 7 through 11 are relevant here. Questions might involve knowledge gained by simulating the single-cycle machine.)
  • Above components, plus
    • Control
    • ALU control
  • Implementation of the five basic instructions.
    • R-type (add, sub, etc.)
    • lw
    • sw
    • beq
    • j
  • Be able to trace through a single-cycle diagram for each instruction.
  • Understand control signals: which ones need to be asserted for a given instruction. (You do not need to memorize the tables that specify control signals, but you should understand how they work, including the reasons for "don't care" entries.)
  • Why the single-cycle implementation is not used.

• Multi-cycle Implementation (Sections 5.4 and 5.6)
  • Above components, plus
    • Instruction register. (Note: We included an "instruction register" component in our single-cycle implementation, but this was not shown in the book's diagrams and was not really a register (did not have state in the single-cycle implementation).)
  • Use of a register between each pair of components, so that there is a latch between clock cycles. Thus the components in order of execution of a lw instruction are: (Latched registers are bold, while other functional units are in italics.)
    • Latched register: PC
    • Component without state: (Instruction) Memory
    • Latched register: Instruction Register
    • Component with state: Register File (read)
    • Latched registers: A and B Registers
    • Component, combinational logic: ALU
    • Latched register: ALUOut Register
    • Component with state: (Data) Memory
    • Latched register: Memory Data Register
    • Component with state: Register File (write)
  • Implementation of basic instructions.
    • R-type (add, sub, etc.)
    • lw
    • sw
    • beq
    • j
  • Five cycles for instructions (only lw needs all five).
  • Be able to trace through a multi-cycle diagram for each instruction. (You should try to have Figure 5.35 more-or-less memorized.)
  • Understand control signals and which are needed. (Not just one set of control signals for each instruction, but different control signals for different cycles of different instructions.)
  • Finite state machine for control (Section 5.4).
    • The new Control component must have state because its outputs (the control signals) depend on the instruction op code and the particular cycle of that instruction.
    • One can use a finite state machine to specify the control.
    • Appendix C talks about implementing this machine (we did not cover this).
    • The book's machine had 10 states (0 through 9) giving all possibilities for each cycle of each instruction.
    • A simple implementation needs an extra state register that holds the current state, so that the outputs can depend on the op code input as well as the previous state number. The next state will also be an output.
  • Advantages of multi-cycle implementation (text, page 377).
    • Can share functional units during different clock cycles, thus saving hardware.
    • Allows instructions with different numbers of (shorter) cycles. (Thus, don't have to make the cycle as long as the longest instruction.)
  • Exceptions and interrupts, in the multi-cycle implementation (Section 5.6)
    • Exceptions (such as overflow or undefined instruction) are internal.
    • Interrupts (such as I/O device request) are external.
    • Implemented either
      • with a single interrupt handler and a cause register to show the reason for the interrupt (as in MIPS), or,
      • with a vectored interrup, where there are different interrupt handlers in a vector for different kinds of causes.
    • The text shows interrupts for overflow or for an undefined instruction. In either case, as extra control signal loads C0 00 00 00, the address of the handler, into the PC. Also set the cause register to 0 for an undefined instruction or to 1 for overflow. MIPS saves the old PC value in another register (EPC register), so that control can be transferred back to the program if desired.
    • Finite state machine for Control unit needs two extra states, 10 and 11.
    • We talked in class about using interrupts to implement new floating point instructions in software, without adding hardware.
• Microprogramming (Section 5.5).
  • Brief discussion of this topic.
  • Microinstructions allow easier implementation of very complex higher-level instructions.
  • Result may be much slower.
  • Examples in class included implementing the same machine model with very different classes of hardware. (As in the IBM 360.)